Current-Mode Analog-to-Digital Converters (iADC)
5 US Patents Issued & Proof of Silicon (Test Forthcoming)
Current-Mode Analog-to-Digital Converter (iADC) Series: The iADC series comprises a patented line of asynchronous current-mode analog-to-digital converters developed for ultra-low-power and cost-efficient applications. Manufactured using standard digital CMOS processes, these converters are designed for continuous, efficient monitoring, supporting smart IoT and near-sensor AI systems.
The iADC converters provide direct interfacing with current-generating sensors, making them well-suited for “always-on” applications and adaptable for current-mode analog neural networks. Initial simulation data is available in preliminary datasheets, with prototypes expected availability by Q4 2024. Evaluation results will follow.
Common Traits of the iADC Family of IP:
- Fast Dynamic Response: Inherent small voltage swings in current-mode signal processing enhance speed.
- Programmable Conversion Speed: Adjustable IDD enables customizable iADC conversion rates.
- Flexible Transfer Function: Programmable reference network allows for linear or non-linear responses.
- Asynchronous Operation: Clock-free and switch-capacitor-free, eliminating related noise and substrate injections.
- Multi-Channel Configurations: Enhanced matching, compact size, and increased speed using patented RBN technology.
- Concurrent Analog & Digital Computation: Mitigates accuracy loss at higher input frequencies.
- No Passive Components: Eliminates capacitors and resistors, reducing silicon costs and enabling ultra-low current operation.
- Broad/Mainstream Digital CMOS Compatibility: Suitable for production on trailing-to-bleeding-edge digital CMOS processes.
- Enhanced Linearity: Calibration or trimming improves accuracy.
- Protected IP: All iADC topologies in this series are patented.








Current-Mode A/D Converter (iADC) Table Simulation Summary (Silicon being Evaluated)
Silicon evaluation work in progress. Data below are based on simulations (please see disclaimers).
Cell Name | TSMC Fab Node | ~Cell Size (µm×µm) | Bits | aVDD High (v) | aVDD Low (v) | IDD (nA) | INL (LSB) | Gain Error (LSB) | AINBW (KHz) | Ƭ (μS) |
---|---|---|---|---|---|---|---|---|---|---|
iADC3_1 | 180nm | 420x180 | 8 | 2 | 1 | 770 | ±1.5 | ±5 | tbd | 8 |
iADC3_2 | 180nm | 580x220 | 8 | 2 | 1 | 1155 | ±2.5 | ±10 | tbd | 38 |
iADC3_3 | 180nm | 250x230 | 8 | 2 | 1 | 880 | ±1.25 | ±5 | tbd | 25 |
iAMP3_4 | 180nm | 290x240 | 8 | 2 | 1 | 885 | ±1.5 | ±10 | tbd | 38 |
iADC4_1 | 180nm | 190x160 | 8 | 2 | 1 | 452 | ±2.3 | ±5 | tbd | 22 |
iADC4_2 | 180nm | 205x140 | 8 | 2 | 1 | 680 | ±2.3 | ±5 | tbd | 33 |
iADC4_3 | 180nm | 345x180 | 8 | 2 | 1 | 2100 | ±0.5 | ±6 | tbd | 4 |
iADC4_4 | 180nm | 335x180 | 8 | 2 | 1 | 850 | ±0.7 | ±4 | tbd | 5 |
Notes: AINBW denotes iADC’s input 3dB bandwidth. Ƭ denotes the transient response of iADC when AIN is pulsed from ¼ scale to ¾ scale. aVDD high and aVDD low denote the maximum and minimum operating range of analog VDD. All iADC Fabricated in low-cost 180nm Digital CMOS. TBD denotes Testing in progress: temperature = 27C, Analog aVDD = 2v, dVDD = 1v. Digital outputs 0→1v. All iADC asynchronous (no clock and no dynamic IDD when AIN not changing)