Current References ≲150nA
5 US Patents Issues & Proof of Silicon
Current References (IREF) with Low Temperature Coefficient (TC): This section contains a number of CMOS ultra-low power (e.g., nano-ampere) IREFs with low TCs. As fundamental building blocks, IREF generally provides the operating current needed for other analog circuits (e.g., amplifiers, voltage references, ADC, DAC, etc.). As such, Ai Analog offers a number of proprietary IREF intellectual property (IP) cells tailored for the different needs of other analog circuits it serves. Besides cell size and current consumption considerations, these needs include less dependence on PMOSFETs vs. NMOSFETs, lower operating VDD vs. lower voltage coefficient, and IREF voltage loop coupled to VDD or VSS, etc. The IREF circuits can also include a start-up and a power-off feature. Some of the common traits of IREF circuits are summarized below. Note that the intellectual property (IP) cells here are generally portable from trailing-edge to bleeding-edge CMOS.
- Tiny CMOS current reference cells with low TC while operating in subthreshold with ultra-low current consumption IDD.
- Large value but tiny active bias resistor (RA) keeps IDD ultra-low.
- IDD and IREF absolute values are mostly a function of MOSFET mobility (µ), which is inherently more stable, helping to narrow current variation over normal fabrication process corners.
- Diverting most leakages (of RA and key FETs) to supplies to improve the temperature range.
- No clock, no switch-capacitor, and no related noise or injections into the substrate.
- Narrow variations over process are also due to IDD and IREF being less sensitive to VTH.
- No passive resistors and no passive capacitors keep the area small and silicon cost low.
- Programmable (pre- or post-silicon) IREF value that also tracks IDD








Current Reference Cell Table Summary
Proof of Silicon Preliminary Specifications (please see disclaimers)
Cell Name | TSMC Fab Node | Cell Size (µm × µm) | VDD High (V) | VDD Low (V) | IDD (nA) | +TC (%/C) | +VC (%/V) | Comments |
---|---|---|---|---|---|---|---|---|
IREF1A | 180nm | 135 × 80 | 2 | 1 | 40 | 0.3 | 0.2 | Utilizes RPMOS, IREF loop coupled to VSS |
IREF2A | 180nm | 96 × 57 | 2 | 0.75 | 40 | 0.2 | 0.3 | Utilizes RNMOS, IREF loop coupled to VSS |
IREF6 | 180nm | 94 × 53 | 2 | 0.7 | 15 | 0.1 | 0.4 | Utilizes RNMOS, IREF loop coupled to VSS |
IREF6A | 180nm | 92 × 52 | 2 | 0.75 | 12 | 0.3 | 0.4 | Utilizes RNMOS, IREF loop coupled to VSS |
IREF7 | 180nm | 76 × 74 | 2 | 0.8 | 43 | 0.2 | 0.3 | Utilizes RPMOS, IREF loop coupled to VDD |
IREF8 | 180nm | 420 × 220 | 2 | 1 | 160 | TBD | TBD | IC Test in progress. Fractional Bandgap IREF (typ~55nA) programmable IREF and TC |
IREF1 | 65nm | 80 × 50 | 1 | 0.7 | 50 | TBD | TBD | IC Test in progress. Utilizes RNMOS, IREF loop coupled to VSS |
IREF2 | 65nm | 70 × 30 | 1 | 0.7 | 74 | TBD | TBD | IC Test in progress. Utilizes RPMOS, IREF loop coupled to VDD |